1. Field of the Invention
This application relates arithmetic structures in computer systems and more particularly to structures utilized in multiplication operations.
2. Description of the Related Art
Computer architectures may include many different types of multiply instructions with various input and output data precision. For example, single instruction multiple data (SIMD) multimedia instructions are typically implemented using partitioned input and output data. Also, in the same implementation, architectures are demanding large 64 bits multiplies.
Conventional floating point units (FPUs) support many data flows customized to a specific multiply instruction to create the best possible performance. By increasing the number of types of multiply data flows implemented independently in a micro-architecture causes the area, power, and costs to grow.
Many multimedia instruction set architectures define several signed and unsigned integer and single precision floating point instructions, which execute as a SIMD (single instruction, multiple data) operation, producing various precision results in parallel.
It would be desirable to implement the various multiplies required by a particular architecture in a single multiplier structure to provide a better area, power, and cost tradeoff for a performance level.